Digital Low Power Base Band Processor for RFID Tags

A low power implementation of a secure EPC UHF passive digital base band processor will be designed for UWB transceiver on RFID for wireless application. To ensure the secure information transaction of the passive tag, traditionally the focus is on directly applying a low complexity encryption engine. The attackers could make use of known header to reveal the secret key. The proposed architecture consists of a novel clock and data flow solution enforced by an anti-collision algorithm engine embedded inside the RFID passive tag. Low power design techniques such as clock gating, optimal clock driving and parallel operation will be used in the design of the tag. The complete digital baseband processor RFID tag consists of a receive and transmit buffer a controller unit to control the data and clock, slot and reset counter ,random generator, comparator and memory controller. Increased power consumption, is one of the important factors, which governs the performance of the ICs in Ultra Deep Sub Micron (UDSM) regime. The hardware model of the complete digital baseband processor will be modeled using verilog HDL code.